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Generating and testing of a RISC-V core - Week 1 of GSoC 2016

As introduced in last week's post, the title of my GSoC 16 project is "RISC-V port to Parallella" so the first thing I had to do was getting familiar with the RISC-V ecosystem. One of the best ways to do so was by viewing some of the recorded videos from the 1st RISC-V Workshop presentations that are available on Youtube. To get up to speed with the most important concepts I recommend the following presentations:

  • Introductions and Welcome (Krste Asanović) [Video] [Slides]
  • RISC-V Software Toolchain (Andrew Waterman) [Video] [Slides]
  • RISC-V “Rocket Chip” SoC Generator in Chisel (Yunsup Lee) [Video] [Slides]
  • Structure of the RISC-V Software Stack (Sagar Karandikar) [Video] [Slides]
  • Debugging on RISC-V (Albert Ou) [Video] [Slides]
  • Porting New Code to RISC-V with OpenEmbedded (Martin Maas) [Video] [Slides]
  • RISC-V Testing Environments (Stephen Twigg) [Video] [Slides]

And some extra ones if you are interested in Chisel, the Scalla-based language that is used to describe the hardware implementations of UCB's RISC-V cores (Rocket with in-order pipe, BOOM with out-of-order pipe and any future ones).

  • Chisel Quick Tutorial (Jonathan Bachrach) [Video] [Slides]
  • Working with Rocket Chip, Adding Extensions, ASIC and FPGA Infrastructure (Colin Schmidt) [Video] [Slides]

If you are deeply interested in RISC-V and the current developments of the community I suggest that you follow up with the rest of the Workshops that were organised (2nd and 3rd) and of-course try to attend the 4th RISC-V Workshop that is happening on July 12-13 in MIT.

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Written by Elias Kouskoumvekakis on Monday May 30, 2016


After surfing the net for two decades and building lots of websites for other people it is at last time to have one of my own!  I kept postponing it for a long time and now that my project proposal for Google Summer of Code 2016 was accepted it was a first class opportunity to create a website and blog about all the interesting stuff that I will be working for the next 3 months. Hopefully I will continue to write even after GSoC 2016 ends since writing about your own stuff is fun!

Google Summer of Code 2016

My proposal for Google Summer of Code 2016 is named "RISC-V port to Parallella" which as the name suggests has to do with successfully porting a RISC-V ISA CPU implementation within the programmable logic (FPGA) of the Xilinx Zynq device of the popular Parallella board. Parallella is an incredibly small (credit-card size) embedded computer for hobbyists and students that can boot a Linux desktop / server on the ARM cores of the Zynq device. Besides Zynq, this board contains an Epiphany chip which is a very capable parallel processor from Adapteva with 16 or 64 core configurations. Thus for the next 3 months (23 May - 23 August) I will be working full-time on a very exiciting (atleast for me!) open-source project and it will be supported by the FOSSi (Free and Open Source Silicon) Foundation which is one of GSoC's participating organizations this year and which selected my proposal (thank you guys!).

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Written by Elias Kouskoumvekakis on Wednesday May 11, 2016