As introduced in last week's post, the title of my GSoC 16 project is "RISC-V port to Parallella" so the first thing I had to do was getting familiar with the RISC-V ecosystem. One of the best ways to do so was by viewing some of the recorded videos from the 1st RISC-V Workshop presentations that are available on Youtube. To get up to speed with the most important concepts I recommend the following presentations:
- Introductions and Welcome (Krste Asanović) [Video] [Slides]
- RISC-V Software Toolchain (Andrew Waterman) [Video] [Slides]
- RISC-V “Rocket Chip” SoC Generator in Chisel (Yunsup Lee) [Video] [Slides]
- Structure of the RISC-V Software Stack (Sagar Karandikar) [Video] [Slides]
- Debugging on RISC-V (Albert Ou) [Video] [Slides]
- Porting New Code to RISC-V with OpenEmbedded (Martin Maas) [Video] [Slides]
- RISC-V Testing Environments (Stephen Twigg) [Video] [Slides]
And some extra ones if you are interested in Chisel, the Scalla-based language that is used to describe the hardware implementations of UCB's RISC-V cores (Rocket with in-order pipe, BOOM with out-of-order pipe and any future ones).
- Chisel Quick Tutorial (Jonathan Bachrach) [Video] [Slides]
- Working with Rocket Chip, Adding Extensions, ASIC and FPGA Infrastructure (Colin Schmidt) [Video] [Slides]
If you are deeply interested in RISC-V and the current developments of the community I suggest that you follow up with the rest of the Workshops that were organised (2nd and 3rd) and of-course try to attend the 4th RISC-V Workshop that is happening on July 12-13 in MIT.