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FSBL changes needed (or not) - Week 6 of GSoC 2016

I am almost certain that since my design had changed Zynq's PS configuration, a new FSBL would be needed. This is due to the addition of extra AXI GP & HPGP ports separate from those that the Parallella Base AXI inteconnect(s) use, since these need to run at a different clock speed (100MHz) than the RISC-V core (50 MHz for RV64IMA or 25 MHz for RV64IMAFD).

Building the FSBL with correct initialization of the new AXI ports and clock is trivial. Unfortunately using it in Parallella is not possible for the end-user without some way to reprogram the flash. I for example have the Xilinx Platform Cable USB II (red box) to do JTAG programming lying around but I don't have a way to connect it to Parallella's JTAG port since it has no pins (the Parallella Porcupine board was made exactly for this purpose, besides easier GPIO). I also have a USB - Serial TTL cable to connect to the 3 serial pins present on Parallella but I don't know if this way of programming the on-board flash is safe and I'm not comfortable doing this with the only Parallella board in my (temporary) possession (courtesy of Philipp - thank you!).

UPDATE: In the end I opted to use an MMCM clock manager to drive the RISC-V clock and thus no extra clock change was needed in the Zynq PS. The extra PS AXI ports as I suspected are always enabled without updating the FSBL. So no FSBL update is needed and thus no Parallella re-flashing (lucky boards - they will live to tell the story of how they handled the mighty RISC-V core!). I updated the previous design post and keep the discussion in this post as a reference for anyone wishing to accomplish what I eventually didn't.

To settle this answer once and for all, my dear mentor Olof K. got me in contact with some Antmicro experts. Here is the answer I received from the Antmicro team (thanks Michael, Karol and Peter!):

How to enable and configure Zynq FPGA device clocks from U-Boot

"Only JTAG method could be considered as safe. If anything goes wrong during reflashing you will end up with a bricked parallela. This may even happen if you flash the board correctly, but your FSBL will be configured wrongly. The only way to revive such a bricked board is to use JTAG and since you do not have access to JTAG port you may have a problem.

The safest, but a little bit more complicated, solution to your issue is to set everything from U-Boot without reflashing. You can use 'mv.l' command to write to a register e.g to a fclk0_ctrl.

If you look at the Zynq TRM (http://www.xilinx.com/support/documentation/user_guides/ug585-Zynq-7000-TRM.pdf) in section B.28 you have all the system level control registers describes. At address 0xF8000170 you have FPGA0_CLK_CTRL.

If you want to set the clock to 100MHz you should run in U-Boot:

mw.l 0xF8000170 0x00100a00

this one is writing 0x00100a00 to register 0xF8000170. It is setting SRCSEL to IOPLL (which is a 1GHz clk) DIVISOR0 to 10 and DIVISOR1 to 1, so the result freq for FCLK0 will be 1000/10/1 = 100 [MHz]

Note that slcr registers are by default write protected. You need to write magic value (0xDF0D) to a UNLOCK_KEY register to unlock them. So the complete procedure of setting fclk0 will be:

mw.l 0xF8000008 0x0000DF0D //unlock slcr
mw.l 0xF8000170 0x00100a00 //set fclk0
mw.l 0xF8000004 0x0000767B //lock slcr

You can set all the required registers in a similar way.

In the end you can write an U-Boot boot script which will set everything before booting the system.

Hint: To access U-Boot prompt on a parallella board remove the mmc card and power up the board. U-Boot will fail to load the system and fall back to a console."

As the above answer implies and of-course I agree, this is the safest solution to set stuff on the PS instead of flashing the board with either serial or Linux methods (JTAG not possible without cable). Even if I myself manage to flash the board it it will be risky and / or not possible without cables for other users to do the same.

Now that setting existing / new clocks is settled, I looked on how to enable the extra PS - PL AXI ports with this method. I couldn't locate anything on the TRM so my conclusion at this point is that these are all enabled by default (clock-gated?) without needing any register setup or FSBL changes, so as long as I drive them with a clock / reset and the AXI signals they should work.

Written by Elias Kouskoumvekakis on Monday July 4, 2016

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