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Parallella - RISC-V FPGA design - Week 5 of GSoC 2016

The Parallella RISC-V FPGA design consists of two major components. The first is the Parallella Base component connected to the ARM cores via AXI4. The Parallella Base component contains the E-Link needed for communication with the Epiphany chip on-board Parallella along with GPIO single ended passthrough (PL <-> PS connections) and I2C bus connection to the on-board power regulators that power mangage the Epiphany chip. Thus the bitstreams produced have identical functionality with those provided by an umodified Parallella.

The other is of-course the RISC-V RV64 core which is generated using the rocket-chip generator. The design supports both the RV64IMA and RV64IMAFD RISC-V architectures. The former is used on the smaller core which doesn't contain an FPU while the latter on the bigger core which does contain an FPU and thus it can execute single or double floating point instructions natively. The default selected core is the smaller RV64IMA so that it can fit on all Parallella editions, regardless of the Zynq FPGA device size they contain.

You can see the design in the following system block diagram of Vivado IP integrator:

RISC-V RV64 AXI Buses

The RISC-V RV64 core communicates with the rest of the ARM SoC of the Zynq FPGA device using AXI4 interfaces:

  • AXI Master: RV64 Core to DDR3 DRAM via ARM (memory access of the core)

  • AXI Slave: ARM to HostIO of RV64 Core (boot / control the core)

Clocking

Finally the Parallella Base component runs with a 100 MHz clock and the RISC-V RV64 core runs with a 50 MHz clock when configured with the IMA extensions or with a 25 MHz clock when configured with the IMAFD extensions.

RISC-V RV64 DRAM Memory

The default allocated DRAM to the RISC-V core is 384 MB, starting from the second half of the 1 GB DDR3 memory of parallella. You can change this by setting the following makefile variables and then rebuilding the bitstream, the device tree for the ARM host and the RISC-V Linux kernel:

  • RISCV_DRAM_BASE_RTL = "3\'d1"
  • RISCV_DRAM_BITS_RTL = 29
  • RISCV_DRAM_BASE_DTS = 0x20000000
  • RISCV_DRAM_SIZE_DTS = 0x18000000
  • RISCV_DRAM_SIZE_LINUX = 384M
./scripts/build.fpga.bitstream.sh
./scripts/build.host.software.sh
./scripts/build.riscv.linux.sh

Please see the previous post which explains the above DRAM makefile variables in more detail.

You can find the Github repository here: https://github.com/eliaskousk/parallella-riscv . You should use the master branch which is (usually!) stable.

Written by Elias Kouskoumvekakis on Monday June 27, 2016

Permalink - Category: news - Tag: gsoc2016

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