It works every time

... 60% of the time


After surfing the net for two decades and building lots of websites for other people it is at last time to have one of my own!  I kept postponing it for a long time and now that my project proposal for Google Summer of Code 2016 was accepted it was a first class opportunity to create a website and blog about all the interesting stuff that I will be working for the next 3 months. Hopefully I will continue to write even after GSoC 2016 ends since writing about your own stuff is fun!

Google Summer of Code 2016

My proposal for Google Summer of Code 2016 is named "RISC-V port to Parallella" which as the name suggests has to do with successfully porting a RISC-V ISA CPU implementation within the programmable logic (FPGA) of the Xilinx Zynq device of the popular Parallella board. Parallella is an incredibly small (credit-card size) embedded computer for hobbyists and students that can boot a Linux desktop / server on the ARM cores of the Zynq device. Besides Zynq, this board contains an Epiphany chip which is a very capable parallel processor from Adapteva with 16 or 64 core configurations. Thus for the next 3 months (23 May - 23 August) I will be working full-time on a very exiciting (atleast for me!) open-source project and it will be supported by the FOSSi (Free and Open Source Silicon) Foundation which is one of GSoC's participating organizations this year and which selected my proposal (thank you guys!).

FOSSi is a non-profit organization with the mission to promote and assist free and open digital hardware designs and their related ecosystems. FOSSi has also started work on LibreCores which hopefully will be a modern successor to the OpenCores website which is starting to look dated and unmaintained. Besides my GSoC project I plan to get invloved in this effort as well. I come from a pure software background with zero hardware knowledge and I know first-hand how difficult it was to get started with hardware design and this project is my chance to further improve on this situation that is still somewhat true.

This is actually my first attempt to work on an open-source project and I'm very happy to finally being able to contribute something back to the community after years of using countless open-source applications and libraries for personal (Linux desktop) and work purposes. Moreover to make sure I succeed within the project's timeframe I will not be alone in this effort. My mentors, Andreas Olofsson and Olof Kindgren are very experienced HW/SW/Embedded engineers and will definitely prove very valuable whenever I need help to proceed with anything unexpected during the project.

To close this post I will place here the abstract of my "RISC-V port to Parallella" project:

With this project I hope to benefit the open-source hardware enthusiast community with work related to the incredible Parallella board used by thousands of students and hobbyists around the world. This project will focus on the integration of the RISC-V rocket core, inside the Zynq FPGA device of Parallella. The RISC-V rocket core is an implementation of the RISV-V ISA that has gotten a lot of attention and support due to being clean, modular and power efficient. This project will allow owners of Parallella boards to write and execute RISC-V programs with minimal effort from their side. The system will work out of the box with a prebuilt binary image ready to be placed in an SD card and users will be able to re-build it with minimal effort. Moreover, a tutorial document will be created to aid inexperienced users make the most of this work and allow them to modify it for their own needs and purposes with custom hardware and / or software code.

Thank you for reading this, now let's have fun!

Written by Elias Kouskoumvekakis on Wednesday May 11, 2016

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Generating and testing of a RISC-V core - Week 1 of GSoC 2016 »

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